GitHub

yosys – Yosys Open SYnthesis Suite

This is a framework for RTL synthesis tools. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. Yosys can be adapted to ...
IEEE

A Novel HDL Code Generator for Effectively Testing FPGA Logic Synthesis Compilers

Abstract: Field programmable gate array (FPGA) logic synthesis compilers (e.g., Vivado, Iverilog, Yosys, and Quartus) are widely applied in electronic design automation (EDA), such as the development ...
GitHub

FPGA MNIST Neural Network Inference

This project implements a complete FPGA inference pipeline for MNIST handwritten digit classification. The system evolves through five progressively refined hardware implementations — from a ...
21ic

Vivado非工程模式下的FPGA设计流程

read_verilog 读入用于非工程模式会话的Verilog(.v)和SystemVerilog(.sv)源文件 read_vhdl 读入用于非工程模式会话的VHDL(.vhd或vhdl)源文件 read_ip 读入用于非工程模式会话的已经存在的IP(.xco或者.xci)工程文件。使用来自.xco IP工程的.ngc网表。对于.xci IP，使用RTL用于编译；或者 ...
IEEE

SCCL: An open-source SystemC to RTL translator

Abstract: We present SCCL, an open-source tool that translates SystemC designs into synthesizable register-transfer level (RTL). SCCL supports a subset of Accellera's SystemC synthesis standard based ...