Configurable behavioral macromodels for amplifiers — voltage op-amps, transimpedance (TIA), and transconductance (Gm) blocks — with one shared equation set across Python, ngspice, and Cadence Spectre.

6 to 10 Yrs All India, Delhi System Verilog Verilog MIPI SATA Ethernet formal verification SOC level test bench verification environment Assertion based verification methodology EDA simulation SV ...

/cores/ Cores library, with Verilog sources, test benches and documentation. /boards/ Top-level design files, constraint files and glue logic. /software/ Basic software for the SoC: libraries + BIOS. ...

VLSI design synthesis LEC lint CDC CLP UPF Verilog VHDL System Verilog RTL design power optimization performance optimization simulation debugging Python Perl IP design IP integration Design Debug ...