EDN

Free phase-locked loop (PLL) analysis software

Editor's Note: Although the primary target market for the 86100CU-400 application presented below is for ASIC/SoC designs, I'm assured by the folks at Agilent that this application is also applicable ...
EDN

Simple SPICE phase locked loop (PLL)

IC designer Don Sauer saw my blog about the difficulties of simulating PLLs and sent me a SPICE file (zip) of a basic PLL that you can play with. Don writes: I have a simple spice netlist for a PLL ...
Hackaday

Unlock The Phase Locked Loop

If you want a stable oscillator, you usually think of using a crystal. The piezoelectric qualities of quartz means that it can be cut in a particular way that it will oscillate at a very precise ...
Electronic Design

Phase-Noise Modeling, Simulation, and Propagation in Phase-Locked Loops (Part 2)

Some brief theory and typical measurements of phase noise. Standard analysis of PLL phase noise used by most CAD applications. How to produce the lowest phase noise at a PLL output. A standard design ...
Hackaday

phase-locked loop

That big grandfather clock in the library might be an impressive piece of mechanical ingenuity, and an even better example of fine cabinetry, but we’d expect that the accuracy of a pendulum timepiece ...
Electronics Weekly

Phase-locked loop triumph

I have always had a soft spot for phase-locked loops – at least, I have since I first found out what they were. What I like about them is that they servo into the best answer for a given situation – ...
Design-Reuse

100MHz-13.5GHz, Gen Phase-Locked Loop (PLL) IP block

Alphacore offers proven 100MHz to 13.5GHz Phase-Locked Loop (PLL) intellectually property (IP) design blocks with the industry's best core offerings w ...
Design-Reuse

TSMC PLL _ Clock Generator / Clock Synthesizer / Phase-Locked Loop, (Fractional / Integer)

The ARKCHIPS PLL is a versatile and stable general-purpose frequency synthesizer with phase synchronization (de-skew) Phase-Locked Loop (PLL) : feed ...
EurekAlert!

Figure 2. Die micrograph of the proposed digital phase locked loop (PLL) (IMAGE)

The total power consumption of the proposed PLL is only 8.89 mW from a 1 V supply, which leads to a figure of merit of reference of -247.4 dB. Credit must be given to the creator. Only noncommercial ...