These days, there is a requirement of achieving high frequency targets with lower power consumption. Achieving both targets simultaneously is very difficult and the situation becomes even more complex ...

In the modern era, where meeting high performance and low power targets for any complex SoC (System on Chip) is very tough, testing the SoC has become even more challenging. The purpose of several DFT ...

For advanced technologies, the industry is seeing very complicated silicon defect types and defect distribution. One consequence is that scan chain diagnosis becomes more difficult. To improve the ...

The complicated silicon defect types and defect distribution of new IC manufacturing technologies can result in very low yield for new designs and technology nodes. During technology qualification ...

To ensure customers receive high-quality products, engineers must consider testing strategies before they even think about a schematic diagram. These days, most engineers realize boundary scan ...

IC designers now have a powerful weapon in the struggle against rising test costs: commercially available EDA solutions that provide fast and effective means to implement scan compression on-chip. By ...