Editor's Note: Although the primary target market for the 86100CU-400 application presented below is for ASIC/SoC designs, I'm assured by the folks at Agilent that this application is also applicable ...

Some brief theory and typical measurements of phase noise. Standard analysis of PLL phase noise used by most CAD applications. How to produce the lowest phase noise at a PLL output. A standard design ...

This application note discusses phase frequency detector characteristics that affect phase-locked loop (PLL) dead band and jitter performance. In PLLs that employ charge pump loop filter designs the ...

Learn about the working principles of Phase-Locked Loops (PLL) and why they are widely used for applications where frequency tracking, resonance driving, and oscillator control are required.

When Hackaday runs a contest, we see all manner of clever projects. But inevitably there are some we don’t see, because their builders didn’t manage to get them finished in time. [Park Frazer]’s phase ...

This is Part 2 of a three-part series. As discussed in Part 1 and recapped here, modern wireless communications systems (mainly superheterodyne radio transceivers) are now required to deliver higher ...

Alphacore offers proven 100MHz to 13.5GHz Phase-Locked Loop (PLL) intellectually property (IP) design blocks with the industry's best core offerings w ...

The total power consumption of the proposed PLL is only 8.89 mW from a 1 V supply, which leads to a figure of merit of reference of -247.4 dB. Credit must be given to the creator. Only noncommercial ...